Priority is claimed from Republic of Korean Patent Application No. 99-65054 filed Dec. 29, 1999, which is incorporated in its entirety by reference.
1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory device. More particularly, the present invention relates to a method of manufacturing a flash memory device capable of minimizing the area of a cell.
2. Description of the Prior Art
A flash memory device is a semiconductor device which find applications in potable electronic products such as PDAs, cellular phones, etc., computer BIOS, a printer, etc. This flash memory device is an electrically erasable and programmable device, which performs program/erase functions by which electrons are moved by a strong electric field with a thin tunnel oxide film of about 100 xc3x85, thus changing the threshold voltage of the cell. Then, the conventional flash memory device will be below explained by reference to FIG. 1.
FIGS. 1A and 1B are a cross-sectional view and an equivalent circuit diagram of a conventional flash memory cell.
As shown in FIG. 1A, the conventional flash memory device has a structure in which a floating gate 12 electrically isolated from a semiconductor device by a tunnel oxide, and a control gate 13 electrically isolated from the floating gate 12 by a dielectric film used to give a high dielectric constant are stacked. Also, a source S region and a drain D region are formed on the semiconductor substrate 11 underlying both sides of the cell. At this time, the tunnel oxide film is formed in thickness of 100 xc3x85 and the control gate 13 acts as a word line of the cell.
Upon a program operation of the flash memory cell having the above mentioned structure, the source S and the semiconductor substrate 11 are grounded (VS=VB=VSS) and a voltage of 9.0V (VCG=9V) is applied to the control gate 13, while a voltage of 5V (VD=5V) is applied to the drain D and the control gate voltage and the drain voltage is applied with a pulse of 5 xcexcs. If a voltage is applied under this condition, channel hot electron (xe2x80x9cCHExe2x80x9d) crosses over the potential barrier of the oxide film to be stored at the floating gate 12, thus completing the program operation. Upon an erase operation, if a negative voltage of xe2x88x929V (VCG=xe2x88x929V) is applied to the control gate 13 and a high voltage of 9V (VD=xe2x88x929V) is applied to the semiconductor substrate 11, electrons stored at the floating gate are flowed out by Fowler-Nordheim tunneling, thus completing the erase operation.
FIG. 1B shows a structure in which the flash memory cell having the above mentioned structure is constructed in a NOR-type cell array.
As shown, the control gates of each of the cells are used as word lines W/L(nxe2x88x921, W/L(n), W/L(n+1) and the drains of each of the cells are used as bit lines B/L(n), B/L(n+1).
In case that this type of NOR-type cell array is constructed, the floating gate storing the charges and the control gate used as the word lines of the cell are formed by mask process. As the channel length and area of the cell is determined by the definition capability of the photography equipments, there is a problem that expensive photography equipments, etc. are required to implement a high-integrated cell in the future. Therefore, in order to manufacture a new flash memory cell, additional advanced technologies are required. Thus, due to additional investment of equipments, there are problems that the manufacturing cost is increased and reduction in investment cost is difficult.
It is therefore an object of the present invention to provide a method of manufacturing a flash memory device that can minimize the areas of a cell and obtain a high-integrated device, by proceeding etching process defining a floating gate with an-isotropic etching process.
In order to accomplish the above object, a method of manufacturing a flash memory device according to the present invention is characterized in that it comprises the steps of, after sequentially forming a pad oxide film and a pad nitride film on a semiconductor substrate, removing a portion of the pad nitride film in which a source formation region will be formed, and then implementing a source ion implantation process; performing a thermal oxidization process to form a device separation film at the portion in which the pad nitride film is removed; removing the pad nitride film and the oxidization film left on the semiconductor substrate and then implementing an ion implantation process for adjusting the threshold voltage; forming a tunnel oxide film and a first polysilicon layer on the semiconductor substrate; etching the first polysilicon layer by an-isotropic etching process to leave first polysilicon only on the sidewalls of the device separation film in the step portion for which the device separation film and the semiconductor substrate make, thus defining a floating gate; and after performing a drain ion implantation process, sequentially forming a dielectric film and a second polysilicon layer for control gate on the entire structure.